1. Field of the Invention
This invention relates generally to data communications and more particularly to deskewing circuits for deskewing multiple pipelined signals.
2. Description of the Related Art
Personal computers (PCs) have gained widespread use in recent years primarily because they are inexpensive and yet powerful enough to handle computationally intensive user applications. The data storage and data sharing capabilities of PCs are often expanded by coupling a group of such computers to peripheral devices such as disk drives, tape drives, and printers. These peripheral devices and the personal computers are interconnected through a single communications network, such as a local area network.
The Small Computer System Interface (SCSI) standard, which is specified by the American National Standards Institute (ANSI X3.131-1986, which is incorporated herein by reference in its entirety) of 1430 Broadway, New York, N.Y. 10018, is an example of an industry-recognized standard for a relatively complex local area network. Descriptions of the SCSI bus may be found for example in U.S. Pat. No. 4,864,291 “SCSI Converter” issued Sep. 5, 1989 to J. E. Korpi and in U.S. Pat. No. 4,905,184 “Address Control System for Segmented Buffer Memory” issued Feb. 27, 1990, to R. P. Giridhar, et al., which are incorporated herein by reference in their entirety.
Using a SCSI network, bit information can be sent from target to target in a serial manner. Generally, data is transmitted along SCSI data lines using analog signal pulses. Upon receiving the signal pulses, the analog signals are converted to digital bits for digital signal processing. However, in addition to sampling input data, the constant clock signal used in accessing the data in subsequent processing is also digitally sampled. Hence, instead of the constant clock being an analog signal having rising and falling edges that can be used for data sampling, the sampled constant clock is a series of bits.
In view of the foregoing, there is a need for bit aligning circuits that provide a bit align mechanism for sampling data using a sampled constant clocked comprised of individual bits. Further, the bit align circuits should allow digital filtering, deskewing, and data reception for any clock speed.